december 2004 dsc-6818/00 1 ?2004 integrated device technology, inc. features 64k x 16 advanced high-speed cmos static ram equal access and cycle times ? automotive: 12/15/20ns one chip select plus one output enable pin bidirectional data inputs and outputs directly lvttl-compatible low power consumption via chip deselect upper and lower byte enable pins single 3.3v power supply available in 44-pin plastic soj, 44-pin tsop, and 48-ball plastic fbga packages description the idt71v016 is a 1,048,576-bit high-speed static ram organized as 64k x 16. it is fabricated using idt?s high-perfomance, high-reliability cmos technology. this state-of-the-art technology, combined with inno- vative circuit design techniques, provides a cost-effective solution for high- speed memory needs and automotive applications. the idt71v016 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. all bidirectional inputs and outputs of the idt71v016 are lvttl-compatible and operation is from a single 3.3v supply. fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. the idt71v016 is packaged in a jedec standard 44-pin plastic soj, a 44-pin tsop type ii, and a 48-ball plastic 7 x 7 mm fbga. functional block diagram output enable buffer address buffers chip enable buffer write enable buffer byte enable buffers oe a 0 ?a 15 row / column decoders cs we bhe ble 64k x 16 memory array sense amps and write drivers 16 low byte i/o buffer 8 8 8 8 i/o 8 i/o 15 i/o 7 i/o 0 6818 drw 01 high byte i/o buffer 3.3v cmos static ram for automotive applications 1 meg (64k x 16-bit) idt71v016sa
6.42 2 idt71v016sa, 3.3v cmos static ram for automotive applications 1 meg (64k x 16-bit) commercial and industrial temp erature ranges 123456 a ble oe a 0 a 1 a 2 nc bi/o 8 bhe a 3 a 4 cs i/o 0 ci/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 dv ss i/o 11 nc a 7 i/o 3 v dd ev dd i/o 12 nc nc i/o 4 v ss fi/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 gi/o 15 nc a 12 a 13 we i/o 7 hnc a 8 a 9 a 10 a 11 nc 6818 tbl 02a pin configurations soj/tsop top view pin description truth table (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 i /o 7 nc a 12 a 13 a 14 a 15 we i /o 6 i /o 5 i /o 4 v ss v dd i /o 3 i /o 2 i /o 1 i /o 0 c s a 0 a 1 a 2 a 3 a 4 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a 6 a 7 oe bhe ble i/o 15 i/o 14 i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 nc a 5 nc so44-1 so44-2 6818 drw 02 note: 1. h = v ih , l = v il , x = don't care. cs oe we ble bhe i/o 0 -i/o 7 i/o 8 -i/o 15 function h x x x x high-z high-z deselected ? standby llh l h data out high-z low byte read l l h h l high-z data out high byte read llh l l data out data out word read lxl l l data in data in word write lxl l h data in high-z low byte write lxl h l high-z data in high byte write l h h x x high-z high-z outputs disabled l x x h h high-z high-z outputs disabled 6818 tbl 02 fbga (bf48-1) top view
6.42 3 idt71v016sa, 3.3v cmos static ram for automotive applications 1 meg (64k x 16-bit) commercial and industrial temp erature ranges absolute maximum ratings (1) recommended operating temperature and supply voltage dc electrical characteristics (v dd = min. to max., automotive temperature ranges) capacitance (t a = +25c, f = 1.0mhz, soj/tsop package) recommended dc operating conditions note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol rating value unit v dd supply voltage relative to v ss ?0.5 to +4.6 v v in , v out terminal voltage relative to v ss ?0.5 to v dd +0.5 v t bias temperature under bias ?55 to +125 o c t j junction temperature page ?40 to +150 o c t stg storage temperature ?65 to +150 o c p t power dissipation 1.25 w i out dc outp ut curre nt 50 ma 6818 tbl 03 grade temperature v ss v dd automotive grade 1 -40c to +125c 0v see below automotive grade 2 -40c to +105c 0v see below automotive grade 3 -40c to +85c 0v see below automotive grade 4 0c to +70c 0v see below 6818 tbl 04 symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v vss ground 0 0 0 v v ih input high voltage 2.0 ____ v dd +0.3 (1) v v il input low voltage ?0.3 (1) ____ 0.8 v 6818 tbl 05 symbol parameter (1) conditions max. unit c in inp ut cap acitance v in = 3dv 6 pf c i/o i/o cap acitance v out = 3dv 7 pf 6818 tbl 06 symbol parameter test conditions automotive temperature grade idt71v016sa unit min. max. |i li | input leakage current v dd = max., v in = v ss to v dd 1 and 2 ___ 5 a 3 and 4 ___ 1 |i lo | output leakage current v dd = max., cs = v ih , v out = v ss to v dd 1 and 2 ___ 5 a 3 and 4 ___ 1 v ol output low voltage i ol = 8ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -4ma, v dd = min. 2.4 ___ v 6818 tbl 07 note: 1. refer to maximum overshoot/undershoot diagram below. the measured voltage at device pin should not exceed half sinusoidal wave with 2v peak and half period of 2ns. maximum overshoot/undershoot v il v ih 6818 drw 12 +2v -2v 2ns 2ns
6.42 4 idt71v016sa, 3.3v cmos static ram for automotive applications 1 meg (64k x 16-bit) commercial and industrial temp erature ranges ac test conditions ac test loads figure 3. output capacitive derating figure 1. ac test load figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow, and t whz ) *including jig and scope capacitance. + 1 . 5 v 50 w i /o z 0 = 50w 6818 drw 03 30pf 6818 drw 04 320 w 350 w 5pf* d ata out 3 . 3 v ( input pulse levels inp ut rise /fall time s input timing reference levels output reference levels ac test load gnd to 3.0v 1.5ns 1.5v 1.5v see figure 1, 2 and 3 6818 tbl 09 parameter 71v016sa12 71v016sa15 71v016sa20 unit symbol automotive grade automotive grade automotive grade 1 2 3 and 4 1 2 3 and 4 1 2 3 and 4 i cc dynamic operating current cs < v lc , outputs open, v dd = max., f = f max (3) max. 110 100 90 80 80 80 80 80 80 ma typ. (4) 75 75 75 70 70 70 70 70 70 i sb dynamic standby power supply current cs > v hc , outputs open, v dd = max., f = f max (3) 45 45 35 35 35 30 30 30 30 ma i sb 1 full standby power supply current (static) cs > v hc , outputs open, v dd = max., f = 0 (3) 552552552ma 6818 tbl 8 dc electrical characteristics (1,2) (v dd = min. to max., v lc = 0.2v, v hc = v dd ? 0.2v, automotive temperature ranges) notes: 1. all values are maximum guaranteed values. 2. all inputs switch between 0.2v (low) and v dd ? 0.2v (high). 3. f max = 1/t rc (all address inputs are cycling at f max ); f = 0 means no address input lines are changing . 4. typical values are measured at 3.3v, 25c and with equal read and write cycles. these parameter is guaranteed by device char acterization but is not production tested.
6.42 5 idt71v016sa, 3.3v cmos static ram for automotive applications 1 meg (64k x 16-bit) commercial and industrial temp erature ranges 71v016sa12 71v016sa15 71v016sa20 symbol parameter min. max. min. max. min. max. unit read cycle t rc read cycle time 12 ____ 15 ____ 20 ____ ns t aa address access time ____ 12 ____ 15 ____ 20 ns t acs chip select access time ____ 12 ____ 15 ____ 20 ns t clz (1,2) chip select low to output in low-z 4 ____ 5 ____ 5 ____ ns t chz (1,2) chip select high to output in high-z ____ 6 ____ 6 ____ 8ns t oe output enable low to output valid ____ 6 ____ 6 ____ 8ns t olz (1,2) output enable low to output in low-z 1 ____ 1 ____ 1 ____ ns t ohz (1,2) output enable high to output in high-z ____ 6 ____ 6 ____ 8ns t oh output hold from address change 4 ? 4 ? 4 ? ns t be byte enable low to outp ut valid ? 6 ? 6 ____ 8ns t blz (1,2) byte enable low to output in low-z 1 ____ 1 ____ 1 ____ ns t bhz (1,2) byte enable high to output in high-z ____ 6 ____ 6 ____ 8ns t pu (3) chip select lo w topower up 0 ____ 0 ____ 0 ____ ns t pd (3) chip select high topo wer down ____ 12 ____ 15 ____ 20 ns write cycle t wc write cycle time 12 ____ 15 ____ 20 ____ ns t aw address valid to end of write 8 ____ 10 ____ 12 ____ ns t cw chip select low to end of write 8 ____ 10 ____ 12 ____ ns t bw byte enable low to end o f write 9 ____ 10 ____ 12 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr address hold from end of write 0 ____ 0 ____ 0 ____ ns t wp write pulse width 8 ____ 10 ____ 12 ____ ns t dw data valid to end of write 6 ____ 8 ____ 9 ____ ns t dh data hold time 0 ____ 0 ____ 0 ____ ns t ow (1,2) write enable high to output in low-z 3 ____ 3 ____ 3 ____ ns t whz (1,2) write enable low to output in high-z ____ 6 ____ 6 ____ 8ns 6818 tbl 10 timing waveform of read cycle no. 1 (1,2,3) notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. oe , bhe , and ble are low. ac electrical characteristics (v dd = min. to max., automotive temperature ranges) data out a ddress 6818 drw 06 t rc t aa t oh t oh data out valid previous data out valid notes: 1. at any given temperature and voltage condition, tchz is less than tclz, tohz is less than tolz, and twhz is less than tow for any given device. 2. this parameter is guaranteed with the ac load (figure 2) by device characterization, but is not production tested. 3. this parameter is guaranteed by design and not production tested.
6.42 6 idt71v016sa, 3.3v cmos static ram for automotive applications 1 meg (64k x 16-bit) commercial and industrial temp erature ranges timing waveform of read cycle no. 2 (1) notes: 1. a write occurs during the overlap of a low cs , low bhe or ble , and a low we . 2. oe is continuously high. if during a we controlled write cycle oe is low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low or bhe and ble low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. timing waveform of write cycle no. 1 ( we controlled timing) (1,2,4) notes: 1. we is high for read cycle. 2. address must be valid prior to or coincident with the later of cs , bhe , or ble transition low; otherwise t aa is the limiting parameter. 3. transition is measured 200mv from steady state. address oe cs data out 6818 drw 07 (3) (3) (3) data valid t aa t rc t oe t olz t chz t ohz out bhe, ble (3) t acs (3) t blz t clz (2) t be t oh t bhz (3) (2) v dd supply current i cc i sb t pd t pu a ddress c s data in 6818 drw 08 (5) (5) (5) data in valid t wc t as t whz (2) t cw t chz t ow t wr we t aw data out t dw t dh previous data valid data valid bhe , ble t bw t wp (5) t bhz (3)
6.42 7 idt71v016sa, 3.3v cmos static ram for automotive applications 1 meg (64k x 16-bit) commercial and industrial temp erature ranges timing waveform of write cycle no. 2 ( cs controlled timing) (1,4) notes: 1. a write occurs during the overlap of a low cs , low bhe or ble , and a low we . 2. oe is continuously high. if during a we controlled write cycle oe is low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low or bhe and ble low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. timing waveform of write cycle no. 3 ( bhe , ble controlled timing) (1,4) address c s data in 6818 drw 09 data in valid t wc t as (2) t cw t wr we t aw d ata out t dw t dh bhe, ble t bw t wp a ddress c s data in 6818 drw 10 data in valid t wc t as (2) t cw t wr we t aw data out t dw t dh bhe, ble t bw t wp
6.42 8 idt71v016sa, 3.3v cmos static ram for automotive applications 1 meg (64k x 16-bit) commercial and industrial temp erature ranges ordering information sa power xx speed xxx package x process/ temperature range 1 2 3 4 automotive grade 1 (-40c to +125c) automotive grade 2 (-40c to +105c) automotive grade 3 (-40c to +85c) automotive grade 4 (0c to +70c) y ph bf 400-mil soj (so44-1) 400-mil tsop type ii (so44-2) 7.0 x 7.0 mm fbga (bf48-1) 12 15 20 71v016 device type i dt speed in nanoseconds 6818 drw 11 x tape & reel 8 x g restricted hazardous substance device
the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 9 idt71v016sa, 3.3v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or ipchelp@idt.com san jose, ca 95138 408-284-8200 800-345-7015 fax: 408-284-2775 www.idt.com rev date page description 0 12/17/04 p. 1-8 released automotive datasheet
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